VIA's P4X266: The Pentium 4 gets DDR
by Anand Lal Shimpi on August 14, 2001 12:00 PM EST- Posted in
- CPUs
The P4X266
It wasn't that difficult for VIA to come up with the design for the P4X266. The North Bridge borrows the AGP 4X controller and V-Link interface from the KT266. The DDR memory controller is taken from the updated (and presently unreleased) revision of the KT266 chipset as well. The only unique part about this chipset is the Pentium 4 bus interface which we can't imagine took VIA all too long to implement in a design.
As with all of VIA's present day offerings, the P4X266 is a two chip solution.
The P4X266 North Bridge is the heart and soul of this chipset. Although it
supports regular SDRAM, almost all P4X266 based solutions will take advantage
of the
Although not officially supported, the chipset will work fine with the 133MHz FSB enabled. This is actually the same case with Intel’s 850 chipset but it’s a rarely used overclock because of the fact that it’s not that easy to get Pentium 4 processors to run at a 33% higher frequency.
The VT8233 South Bridge is the same V-Link enabled
The two chips are connected by VIA’s 8-bit V-Link bus that is capable of transferring at up to 266MB/s.
There is nothing fundamentally new about the P4X266 which is why it’s not surprising that VIA was able to go from beta to production silicon so quickly. If you’ll remember from our Computex coverage, the first time VIA had ever publicly shown and benchmarked the P4X266 was in front of right us at their Computex press conference. Almost two months later, VIA is ready to begin shipments of the part to motherboard manufacturers. There are even a few bigger name manufacturers that already have boards ready and should be able to offer them in a reasonable timeframe.
VIA will be introducing a pin compatible version of the P4X266 North Bridge with integrated S3 Savage video. This will be called the P4M266. The P4X266 supports both Socket-423 and Socket-478 processors as well as the upcoming Northwood core (0.13-micron Pentium 4).
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